1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a read only memory.
2. Description of the Related Art
As the function of a microprocessor becomes more powerful and the amount of computation being processed by software programs increases, required memory capacity increases correspondingly. Therefore, fabricating high-capacity and low-cost memories is an important subject for the semiconductor manufacturers. The memories are simply classified into two types, which are read only memory (ROM) and random access memory (RAM) according to the read/write functions. A ROM can only perform reading functions. A RAM can further perform reading the writing functions. According to the methods for data storage, ROMs can be further classified into, for example mask ROMs, programmable ROMs (PROM), erasable programmable ROMs (EPROM), electrically erasable programmable ROMs (EEPROM), etc. According to the data processing function, RAMs can be classified into static RAMs (SRAM) and dynamic RAMs (DRAM).
ROMs are widely used in mini-computers, microprocessor systems, and other digital devices for storing system information and the terminate and stay resident (TSR) programmers such as BIOS. Since the fabrication of a ROM is very complicated, and includes numerous time-consuming processes and preparations for materials, the manufacturers normally code the needed programs and information from customers into memories during the fabrication process.
Since the rest of the structures, with the exception of the information stored during the programming process, are the same for most ROMs, partially finished ROMs are usually stocked at the stage before the programming process. After a specific program is given by customers, the required photomask is formed in order to store the program codes into the partially finished ROMs. In this manner, the whole fabrication process of the ROM can be quickly finished. The foregoing method, which is also known as a post-programming mask-type ROM method, is frequently used in industry.
A channel transistor is normally used as a memory cell in a ROM. Within the programming process, dopants are selectively implanted into certain channels to modify the threshold voltage in order to control the on/off state of a memory cell. A ROM includes a polysilicon word line WL bridging over a bit line BL, and a channel of a memory cell between bit lines BL and under the word line WL. In the ROM, the stored binary data, 0 or 1, is dependent on whether or not the channel has ions implanted.
FIGS. 1 to 3 schematically illustrate the representation of the conventional method for fabricating a PROM, wherein FIG. 1 is a schematic, top-view layout showing a conventional PROM, FIG. 2 is a schematic, cross-sectional view of FIG. 1 taken along line I--I, and FIG. 3 is a schematic, cross-sectional view of FIG. 1 taken along line II--II.
Referring to FIGS. 1, 2, and 3, a pad oxide layer (not shown) is formed on a substrate 10 by thermal oxidation. A field oxide layer 14 is formed in the substrate 10 by local oxidation for defining the active areas on the substrate. A wet etching is performed to remove the pad oxide layer. An oxide layer 12 is formed next to the field oxide layer 14 by thermal oxidation. A first polysilicon layer is formed on the oxide layer 12 by low-pressure chemical vapor deposition. A photolithographic and etching process is performed on the first polysilicon layer to form a first polysilicon layer 16.
An inter-poly dielectric layer (not shown) is formed on the first polysilicon layer 16 by low-pressure chemical vapor deposition. Then, a second polysilicon layer (not shown) is formed on the inter-poly dielectric layer by low-pressure chemical vapor deposition. A photolithographic and etching process is performed to pattern the second polysilicon layer and the inter-poly dielectric layer. A second polysilicon layer 20 and an inter-poly dielectric layer 18 are formed.
A photolithographic and etching process is performed with the second polysilicon layer 20 as a mask. The polysilicon layer 16 is patterned. The second polysilicon layer 20 again as a mask to implant ion with a high concentration. An implanted region 22 is formed in the substrate 10. A dielectric layer 24 is formed over the substrate 10 by low-pressure chemical vapor deposition. A contact opening 26 is formed in the dielectric layer 24 by a photolithographic and etching process. A metallic layer 28 is formed to fill the contact opening 26 and electrically couple with the implanted region 22. The metallic layer 28 is sued as a bit line. Some follow-up steps are performed to complete a PROM.
In the conventional method described above, it is difficult to fabricate a PROM with a further reduction in size because the reduction of the contact opening is limited. Moreover, the existence of the field oxide layer affects the size reduction of a PROM and surface planarization. Because the surface varies in different regions, it is difficult to obtain etching uniformity in the dry etching step, which causes difficulty in determining the etching time. In addition, the contact opening 26 is filled with metallic layer 28 for forming a bit line. Thus, reflection interference of a metallic layer 28 cannot be avoided.
Another conventional method thus is provided to reduce the size of a PROM, which comprises forming buried bit line under the field oxide layer. But difficulty is still encountered with the existence of a field oxide layer in this method. Thus, the size reduction is limited and the planarization is still poor. Moreover, the field oxide layer lies over a buried bit line, which makes a self-aligned process for forming a bit line difficult to perform.